Media Summary: In this video, our research work is presented: “RAMAN: Resource-efficient ApproxiMate Posit Processing for Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ... AI workloads, spanning edge intelligence to large language models (LLMs), are placing unprecedented demands on computing ...

An Algorithm Hardware Co Design - Detailed Analysis & Overview

In this video, our research work is presented: “RAMAN: Resource-efficient ApproxiMate Posit Processing for Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ... AI workloads, spanning edge intelligence to large language models (LLMs), are placing unprecedented demands on computing ... Webinar Archive – Now Available! In this webinar, Prof. Priyadarshini (Priya) Panda, from the Intelligent Computing Lab at Yale ... Presentation at FCCM 2020. Authors: Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang and Jason ... Abstract: As the silicon technology approaches the Post-Moore's Law Era,

AI is reshaping every workflow, and the breakthrough enabling this shift is extreme The shift toward multi-core processors is the most obvious implication of a greater trend toward efficient computing. In the past ... More accurate machine-learning requires larger models – but large models pose problems both in the training and inference ... Keynote by Prof. Deming Chen, UIUC (VAST Lab Alumni) at ROAD4NN Workshop. Originally posted at ... IEEE Communication Society (ComSoc) New York Chapter Seminar Tuesday Nov 30, 2021 7pm – 8pm Eastern Time (US ... This talk was part of SNUFA 2022. See more at

Algorithm Hardware & Core Design 10xTalks This talk is part of the Scientific Machine Learning Research Talks (SMaRT) Seminar Series, a joint initiative between Johns ...

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RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN
Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT
HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability
Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)
DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead
Algorithm-Hardware Co-Design for BQSR Acceleration in Genome Analysis ToolKit
Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration
How Extreme Hardware–Software Co-Design Is Driving the Future of AI Supercomputing
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design
Hardware-Software Co-Design for General-Purpose Processors  [1/14]
HiPEAC22 Keynote 1: Efficient Machine Learning: Algorithms-Hardware Co-design – Hai 'Helen' Li
An Algorithm Hardware Co Design for Bayesian Neural Network Utilizing SOT MRAM’s Inherent Stochastic
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RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN

RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm–Hardware Co-desigN

In this video, our research work is presented: “RAMAN: Resource-efficient ApproxiMate Posit Processing for

Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT

Ep 13: Energy-efficient Algorithm-hardware Co-design with Dr. Vivienne Sze, MIT

Dr. Vivienne Sze is an associate professor in the EECS department at MIT. Vivienne is recognized for her leading work on ...

Sponsored
HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability

HiPEAC 2026 keynote 3: AI and hardware co-design: Taming quality, productivity, and reliability

AI workloads, spanning edge intelligence to large language models (LLMs), are placing unprecedented demands on computing ...

Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)

Biologically Inspired Algorithm & Hardware Co-Design | Prof. Priya Panda (Yale University)

Webinar Archive – Now Available! In this webinar, Prof. Priyadarshini (Priya) Panda, from the Intelligent Computing Lab at Yale ...

DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead

DAC Paper Review: Algorithm/Hardware Co-Design for In-Memory Computing with Minimal Circuit Overhead

My review of the paper presented at DAC:

Sponsored
Algorithm-Hardware Co-Design for BQSR Acceleration in Genome Analysis ToolKit

Algorithm-Hardware Co-Design for BQSR Acceleration in Genome Analysis ToolKit

Presentation at FCCM 2020. Authors: Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang and Jason ...

Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration

Efficient Algorithm-Hardware Co-Design Methodology for Quantized LLM Acceleration

Abstract: As the silicon technology approaches the Post-Moore's Law Era,

How Extreme Hardware–Software Co-Design Is Driving the Future of AI Supercomputing

How Extreme Hardware–Software Co-Design Is Driving the Future of AI Supercomputing

AI is reshaping every workflow, and the breakthrough enabling this shift is extreme

ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design

ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design

ASAP 2021 15 minutes presentation.

Hardware-Software Co-Design for General-Purpose Processors  [1/14]

Hardware-Software Co-Design for General-Purpose Processors [1/14]

The shift toward multi-core processors is the most obvious implication of a greater trend toward efficient computing. In the past ...

HiPEAC22 Keynote 1: Efficient Machine Learning: Algorithms-Hardware Co-design – Hai 'Helen' Li

HiPEAC22 Keynote 1: Efficient Machine Learning: Algorithms-Hardware Co-design – Hai 'Helen' Li

More accurate machine-learning requires larger models – but large models pose problems both in the training and inference ...

An Algorithm Hardware Co Design for Bayesian Neural Network Utilizing SOT MRAM’s Inherent Stochastic

An Algorithm Hardware Co Design for Bayesian Neural Network Utilizing SOT MRAM’s Inherent Stochastic

An Algorithm Hardware Co Design

Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators  (ROAD4NN)

Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators (ROAD4NN)

Keynote by Prof. Deming Chen, UIUC (VAST Lab Alumni) at ROAD4NN Workshop. Originally posted at ...

Algorithm and Hardware Co-Design for Energy-Efficient Deep Learning

Algorithm and Hardware Co-Design for Energy-Efficient Deep Learning

IEEE Communication Society (ComSoc) New York Chapter Seminar Tuesday Nov 30, 2021 7pm – 8pm Eastern Time (US ...

SAFARI Live Seminar - Software-Hardware Co-design of Edge AI Systems

SAFARI Live Seminar - Software-Hardware Co-design of Edge AI Systems

Title: Software-

Priya Panda - Algorithm-Hardware Co-design for Efficient and Robust Spiking Neural Networks

Priya Panda - Algorithm-Hardware Co-design for Efficient and Robust Spiking Neural Networks

This talk was part of SNUFA 2022. See more at http://snufa.net/2022/

Algorithm Hardware & Core Design | 10xTalks

Algorithm Hardware & Core Design | 10xTalks

Algorithm Hardware & Core Design | 10xTalks

Software Hardware Co-Design DA2 - Rolano A. Rebelo(2/2)

Software Hardware Co-Design DA2 - Rolano A. Rebelo(2/2)

Software

Bio-Inspired Algorithm & Hardware Co-Design for Efficient AI | Dr. Priya Panda | JHU-IITD SMaRT

Bio-Inspired Algorithm & Hardware Co-Design for Efficient AI | Dr. Priya Panda | JHU-IITD SMaRT

This talk is part of the Scientific Machine Learning Research Talks (SMaRT) Seminar Series, a joint initiative between Johns ...

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